探索类脑与具身智能前沿应用领域

近期学校组织开展了2026年度优秀博士学位论文评选工作。经校学位评定委员会审定，集成电路学院吴子涵博士生的学位论文获评“北京大学2026年优秀博士学位论文”。

The university recently launched the selection of the 2026 Excellent Doctoral Dissertations. Upon review and approval by the University Academic Degrees Committee, the doctoral dissertation by Wu Zihan, a PhD candidate from the School of Integrated Circuits, has been honored as one of the "2026 Excellent Doctoral Dissertations of Peking University".

本文设计心智融合 Transformer 作为教师模型，引入认知先验知识引导视觉特征学习；同时训练轻量化学生模型，仅依靠图像输入即可复刻教师模型的认知引导特征。依托双层优化策略，教师模型学习具备天然可蒸馏性的特征表征，使学生模型能够高效复现认知层面的视觉引导效果。大量对比实验表明，本文所提方法取得当前最优的图像融合效果，输出结果与人眼主观感知高度契合。

A Mental Integrated Transformer serves as the Teacher, incorporating cognitive priors to guide visual feature learning, while a lightweight Student is trained to approximate these cues using only image inputs. Through bi-level optimization, the Teacher learns inherently distillable representations, enabling the Student to emulate cognitive guidance efficiently. Extensive experiments confirm that our method achieves state-of-the-art fusion performance and aligns more closely with human perception

本文提出了一款面向CNN与SNN融合计算的异构加速器EA-HWP。针对权重分布的高斯特性，设计了稠密-稀疏计算架构：稠密部分采用可重构脉动阵列计算2-bit低精度权重，稀疏部分采用可重构交叉阵列计算8-bit高精度权重，在模型精度与推理能效间取得良好平衡。芯片同时集成256个CNN神经元与256个SNN神经元，支持CNN计算、CNN-SNN转换与SNN计算三种模式。在28nm CMOS工艺下，CNN模式最高频率1152MHz，能效0.14pJ/OP；SNN模式最高频率792MHz，能效0.26pJ/SOP。在MNIST、CIFAR-10、CIFAR-100数据集上验证了混合精度与混合模型的有效性。

This paper presents EA-HWP, a heterogeneous CNN/SNN accelerator for fusion computing. Leveraging the Gaussian distribution of weights, a dense-and-sparse computing architecture is proposed: the dense part uses a reconfigurable systolic array for 2-bit low-precision weights, while the sparse part uses a reconfigurable crossbar for 8-bit high-precision weights, balancing model accuracy and inference energy. The chip integrates 256 CNN neurons and 256 SNN neurons, supporting CNN computation, CNN-SNN conversion, and SNN computation. Fabricated in 28nm CMOS, EA-HWP achieves a maximum frequency of 1152MHz for CNN with 0.14pJ/OP energy efficiency, and 792MHz for SNN with 0.26pJ/SOP. Its effectiveness is validated on MNIST, CIFAR-10, and CIFAR-100 datasets.

2026年4月，实验室助理研究员钟毅线下参加了在美国西雅图举办的IEEE CICC 2026国际会议，并作口头报告，介绍了本项研究成果。会上与来自学术界和工业界的专家学者就SNN-ANN统一训练架构、分布式多核学习、自适应内存组织等前沿问题进行了深入交流。

2026年4月，实验室助理研究员钟毅线下参加了在美国西雅图举办的IEEE CICC 2026国际会议，并作口头报告，介绍了本项研究成果。会上与来自学术界和工业界的专家学者就SNN-ANN统一训练架构、分布式多核学习、自适应内存组织等前沿问题进行了深入交流。

2026年4月，实验室博士生张桃线下参加了在美国西雅图举办的IEEE定制集成电路会议（CICC 2026），并作口头报告，介绍了本项研究成果。会上与来自学术界和工业界的专家学者就能效加速器设计、事件相机光流估计的硬件优化等前沿问题进行了深入交流。

In April 2026, Tao Zhang, a Ph.D. student of the lab, attended the IEEE Custom Integrated Circuits Conference (CICC 2026) in Seattle, USA, and delivered an oral presentation on this work. He engaged in in-depth discussions with experts and scholars from academia and industry on cutting-edge topics such as energy-efficient accelerator design and hardware optimization for event-camera-based optical flow estimation.

本文提出了PAICORE类脑处理器芯片，采用1024核分布式架构，集成191.9万神经元与47.73亿突触，支持SNN推理、ANN推理与片上STDP学习三种范式的统一。芯片采用五级胖四叉树NoC与GALS时钟设计，通过可重构计算核心实现多范式无缝交互。在28nm CMOS下，SNN峰值性能20.74TSOPS，能效5.181TSOPS/W；ANN峰值41.49TOPS，能效10.372TOPS/W；片上学习能效1.222TSOPS/W。配合PAIFLOW软件框架，可高效部署大规模多任务边缘智能应用。

This paper introduces PAICORE, a 1024-core neuromorphic processor integrating 1.919 million neurons and 4.773 billion synapses. It unifies SNN inference, ANN inference, and on-chip STDP learning into a reconfigurable architecture. A five-level fat quadtree NoC and GALS design enable efficient data communication. Fabricated in 28nm CMOS, PAICORE achieves peak SNN performance of 20.74 TSOPS at 5.181 TSOPS/W, ANN performance of 41.49 TOPS at 10.372 TOPS/W, and on-chip learning efficiency of 1.222 TSOPS/W. The PAIFLOW software framework facilitates large-scale deployment for edge intelligence tasks.

本文提出了一款面向雷达辐射源识别（REC）的高效能类脑处理器NeuroREC。针对雷达信号天然适合脉冲神经网络（SNN）处理的特点（信号幅值多数时间较低、噪声环境下鲁棒性强），芯片采用单核设计，集成1024个轴突与256个树突，支持8-bit权重精度。提出了D-CSR稀疏权重压缩算法与对应的权重重化解码电路，结合有效脉冲检测电路与细粒度流水线，大幅提升能效。创新性引入乒乓运行机制（PPRM），解决大模型部署时IO吞吐与片上计算速率不匹配的问题。在28nm CMOS工艺下，芯片面积1.20mm²，在特定稀疏条件下峰值能效达7.22TSOP/W，对RadioML2016.b与RadioML2018.a数据集分类精度与鲁棒性均优于传统CNN。

This paper presents NeuroREC, an efficient neuromorphic processor for radar emitter classification (REC). Recognizing that radar signals naturally match spiking neural networks (SNNs) due to their low average amplitude and inherent robustness against noise, the chip adopts a single-core design integrating 1024 axons and 256 dendrites with 8-bit weight precision. A D-CSR sparse weight compression algorithm and corresponding weight decompression circuitry are proposed, together with a valid spike detection circuit and fine-grained pipeline to significantly improve energy efficiency. A ping-pong running mechanism (PPRM) is introduced to address the mismatch between I/O throughput and on-chip computation when deploying large SNN models. Fabricated in 28nm CMOS with a 1.20mm² die area, NeuroREC achieves a peak energy efficiency of 7.22 TSOP/W under specific sparsity conditions, and demonstrates superior accuracy and robustness on RadioML2016.b and RadioML2018.a datasets compared to conventional CNNs.

本文提出了一款面向脉冲神经网络（SNN）与事件驱动人工神经网络（event-based ANN）的通用类脑计算芯片。芯片采用8×8网格的64个神经突触核，集成64K神经元与64M 1-bit突触，所有存储单元均片上集成。基于数字LIF神经元模型与点对点AER路由协议，支持灵活的网络拓扑与时空编码。在65nm CMOS工艺下，峰值能效达2.64pJ/SOP（@0.89V，24MHz），峰值吞吐量12.29GSOP/s。在CIFAR-10和SVHN数据集上验证了CNN与时空记忆模型的兼容性。

This paper presents a general-purpose neuromorphic chip for spiking neural networks (SNNs) and event-driven ANNs. It integrates 64K neurons and 64M 1-bit synapses in an 8×8 core array, with all memory on chip. Based on a digital LIF neuron model and point-to-point AER routing, it supports flexible topologies and spatio-temporal coding. Fabricated in 65nm CMOS, the chip achieves a peak energy efficiency of 2.64pJ/SOP (@0.89V, 24MHz) and peak throughput of 12.29GSOP/s. CNN and spatio-temporal memory models are validated on CIFAR-10 and SVHN datasets.

2021年5月，实验室博士生匡毅松线上参加了在韩国大邱举办的IEEE国际电路与系统研讨会（ISCAS 2021），并在会上报告了本项研究成果。会上与各国学者就类脑芯片对人工神经网络的兼容性、时空编码方案等议题进行了深入交流。

In May 2021, Yisong Kuang, a Ph.D. student of the lab, participated online in the IEEE International Symposium on Circuits and Systems (ISCAS 2021) held in Daegu, South Korea, and presented this work. He engaged in in-depth discussions with international scholars on topics such as the compatibility of neuromorphic chips with artificial neural networks and spatio-temporal coding schemes.

2021年5月，实验室博士生钟毅线上参加了在韩国大邱举办的IEEE国际电路与系统研讨会（ISCAS 2021）。会上展示了团队在类脑计算与脉冲神经网络硬件加速方面的最新研究成果，与来自全球的学者就低功耗神经形态芯片设计、片上学习算法等前沿问题进行了深入交流与讨论，拓宽了研究视野，促进了国际合作。

In May 2021, Yi Zhong, a Ph.D. student of the lab, participated online in the IEEE International Symposium on Circuits and Systems (ISCAS 2021) held in Daegu, South Korea. He presented the team's latest research progress in neuromorphic computing and spiking neural network hardware acceleration. In-depth discussions were held with global scholars on cutting-edge topics such as low-power neuromorphic chip design and on-chip learning algorithms, which broadened research perspectives and fostered international collaboration.